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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.9k 1.3k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.9k 306

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.4k 397

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 966 245

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 748 180

Repositories

Showing 10 of 122 repositories
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible's past year of commit activity
    C++ 1,934 306 564 (16 issues need help) 33 Updated Sep 13, 2026
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl's past year of commit activity
    SystemVerilog 155 Apache-2.0 107 112 (2 issues need help) 41 Updated Sep 13, 2026
  • usb2 Public

    USB core

    chipsalliance/usb2's past year of commit activity
    VHDL 1 Apache-2.0 6 12 4 Updated Sep 13, 2026
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog's past year of commit activity
    C++ 474 Apache-2.0 90 47 (2 issues need help) 0 Updated Sep 13, 2026
  • rocket-chip Public

    Rocket Chip Generator

    chipsalliance/rocket-chip's past year of commit activity
    Scala 3,864 1,298 271 76 Updated Sep 13, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator's past year of commit activity
    SystemVerilog 44 908 0 0 Updated Sep 12, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw's past year of commit activity
    Rust 166 Apache-2.0 127 238 (8 issues need help) 76 Updated Sep 12, 2026
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw's past year of commit activity
    Rust 38 Apache-2.0 86 163 (5 issues need help) 82 Updated Sep 11, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests's past year of commit activity
    SystemVerilog 394 ISC 103 47 (4 issues need help) 37 Updated Sep 11, 2026
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge's past year of commit activity
    SystemVerilog 63 Apache-2.0 17 17 4 Updated Sep 11, 2026
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